This invention relates to a semiconductor memory cell, and a method of fabrication thereof, and a semiconductor memory cell array.
Semiconductor memory cells which comprise a single transistor and a single capacitor (hereinafter referred to as a 1T cell) has been used for a high integrated semiconductor memory. In general, it is desired that the 1T cell has a large output voltage and a small area for high integration. An output voltage of the 1T cell is approximately proportional to C.sub.S /(C.sub.S +C.sub.B), where C.sub.S is the cell capacitance and C.sub.B is the parasitic capacitance between the bit-line and a semiconductor substrate. To realize high integration, it is preferable that the 1T cell has a small area but a large capacitance. Further, it is desirable that a bit-line has a small parasitic capacity.
Such a 1T cell having a small area and a large capacitance has been proposed. For instance, a 1T cell including a stacked capacitor (hereinafter referred to as a stacked capacitor cell) is one Example. A stacked capacitor cell is disclosed in T. Ema at al., 1988 International Electron Devices Meeting p.592 "3-dimensional stacked capacitor cell for 16M and 64M DRAMs".
FIGS. 1A and 1B illustrate the stacked capacitor cell which comprises a transistor and a stacked capacitor having two fins 17a and 17b provided on a substrate 1. In FIG. 1B, a capacitor comprises an electrode having the two fins 17a and 17b, a capacitive insulation film (not shown) and an opposite electrode 19. A structure of the two fins 17a and 17b permits the stacked capacitor to have a high capacitance on a small area due to a large interface of the electrodes. While, the transistor comprises two diffusion regions serving as source/drain regions 14-1 and 14-2, and a word-line 13 serving as a gate. A layer 12 may serve as a gate insulation layer. A bit-line 20 is in contact with either the source region or the drain region. Layers 8, 12, 21 and 22 serve as insulation layers respectively. A layer 23 serves as a protection layer.
It is, therefore, understood that the set forth stacked capacitor cell has a large capacitance over a small occupied area, which is suitable for high integrated semiconductor memories. The stacked capacitor cell has, however, a problem in an arrangement of a capacitor contact hole CO2 between the transistor and the stacked capacitor. The capacitor contact hole is so arranged as not to contact with the bit-lines and the word-lines. Further, the capacitor contact hole is filled with a conductive material to form a capacitor contact. To realize a higher integration, it is required that the contact hole have a diameter as small as possible and arrange-s in the vicinity of the word-line 13 and the bit-line 20. Further, the contact hole is required to have a large depth due to the insulation layers 21 and 22. It is, however, difficult to fill the very slender contact hole with the conductive material.
To combat the set forth problems in the arrangement of the capacitor contact hole, a memory cell was proposed in which a bit-line is buried in an isolation region. One such memory cell is disclosed in 1990 Symposium on VLSI Technology, Y. Kohyama at al., "Buried Bit-Line Cell for 64 MB DRAMs". In this memory cell, the contact hole between a bit-line and one of transistor source/drain electrodes is formed in the insolation region. While, the contact hole between a capacitor and another transistor source/drain electrodes is formed in the insulation layer in the same way of the set forth memory cell.
In the memory cell, the capacitor contact hole is so aligned as not to contact with the word-line only because the bit-line is buried in the isolation region, thereby substantially reducing the difficulty in the arrangement of the capacitor contact hole.
The memory cell is, however, engaged with another problem in a large parasitic capacity between the bit-line and the semiconductor substrate. The bit-line buried in an isolation region is surrounded by the insulation material, thereby resulting in a large parasitic capacity between the bit-line and the semiconductor substrate. The large parasitic capacity is undesired to have a required output voltage on a small memory cell area which is suitable for higher integration. The large parasitic capacity is also undesirable for a high speed performance of the memory. The large parasitic capacity is also associated with a bit-line length. It is, thus, desirable to reduce the bit-line length.
On the other hand, to combat the set forth problem in the arrangement of the capacitance contact hole for high integration, it may also be considered that the bit-line and the word-line are taken into a smaller width and thickness. Such a bit-line and word-line, however, have a relatively large resistance which is undesirable for high speed performance of the memory Further, the bit-line is made of a material having a relatively large specific resistance.
To realize a higher integration, it is required that many memory cells are integrated. This, however, requires a large bit-line length which provide the undesired large parasitic capacitance and large resistance thereof. In general, the large resistance and the parasitic capacity of the bit-line are also associated with the length thereof. It is, then, desired to reduce the bit-line and word-line length. If it is not so, many bit-lines and sense amplifiers are required thereby preventing a higher integration.
In addition, when a bit-line arrangement is taken into a very small pitch for the higher integration, a problem in a noise caused by a parasitic capacity between bit-lines is considerable. Such a noise caused by the parasitic capacity between bit-lines provides undesirable influences to a bit-line signal read performance. It is, therefore, desirable to reduce and shield such a bit-line noise. The bit-line noise is also associated with a parasitic capacity between bit-lines. It is also desirable for a noise reduction to reduce the parasitic capacity between bit-lines.